Memory circuit with leakage compensation

ABSTRACT

A memory array comprising a word line and a bit line is disclosed. Each of a plurality of memory cells of the memory array has a first terminal connected to the bit line and a current path between the first terminal and a respective second terminal. A first memory cell of the plurality of memory cells has the second terminal coupled to receive a first supply voltage when selected by the word line. A second memory cell of the plurality of memory cells has the second terminal coupled to receive a voltage different from the first supply voltage when the first memory cell is selected by the word line.

BACKGROUND OF THE INVENTION

The present embodiments relate to a memory circuit with leakagecompensation of unselected memory cells.

Shrinking semiconductor integrated circuit feature sizes have placedincreasing challenges on semiconductor integrated circuit design. Inparticular, minimum feature sizes of high density memory cells arefrequently less than corresponding feature sizes of peripheral circuits.As a result, leakage current in unselected memory cells (I_(LEAK)) mayadversely affect correct sensing of a selected memory cell on a commonbit line. This is particularly true of nonvolatile memories such asFlash EEPROM and ROM memories. However, this undesirable leakage currentmay also adversely affect standby current of volatile SRAM memories.Moreover, undesirable leakage current may compromise operation of bothembedded memories in System on Chip (SoC) applications as well asstand-alone memories. Thus, there is a need to reduce leakage current inunselected memory cells for both nonvolatile and volatile memorysystems. Accordingly, embodiments of the present invention describedbelow are directed toward this and other improvements over the priorart.

BRIEF SUMMARY OF THE INVENTION

In a first embodiment of the present invention, there is disclosed amemory array having a word line and a bit line. Each of a plurality ofmemory cells of the memory array has a first terminal connected to thebit line and a current path between the first terminal and a respectivesecond terminal. A first memory cell of the plurality of memory cellshas the second terminal coupled to receive a first supply voltage whenselected by the word line. A second memory cell of the plurality ofmemory cells has the second terminal coupled to receive a voltagedifferent from the first supply voltage when the first memory cell isselected by the word line

In a second embodiment of the present invention, there is disclosed aplurality of memory cells. Each memory cell has a first terminal, asecond terminal, and a control terminal arranged to control current flowbetween the respective first and second terminals. A plurality of bitlines are connected to first terminals of respective memory cells. Abias circuit is arranged to apply a supply voltage to the secondterminals of the memory cells in a first mode of operation and to applya bias voltage different from the supply voltage to the second terminalsin a second mode of operation.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a diagram of an exemplary memory circuit according to thepresent invention;

FIG. 2 is a simplified circuit diagram of memory blocks 106 and 108 ofFIG. 1;

FIG. 3 is a circuit diagram of source line (SL) bias circuits 104 and110 of FIG. 1 coupled to respective memory blocks 106 and 108;

FIG. 4 is a circuit diagram showing operation of memory sector 102 ofFIG. 1 during a memory read operation according to the presentinvention; and

FIG. 5 is a timing diagram showing operation of memory sector 102 ofFIG. 4 during the memory read operation.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, there is a diagram of an exemplary memory circuit100 according to the present invention. The memory circuit, oftenreferred to as a macro, may be used for a System on a Chip (SoC),embedded memory, or stand alone memory applications. The diagram showsfour memory sectors 102, 120, 130, and 140. Additional memory sectorsmay be included as indicated by ellipses. Each memory sector issubstantially the same, so only memory sector 102 will be described indetail. In the following discussion, the same reference numerals areused to describe substantially the same circuit elements. Memory sector102 includes memory blocks 106 and 108 and respective source line biascircuits 104 and 110 as will be described in detail. Each memory blockincludes N word lines (WL) and M bit lines (BL), where N and M arepositive integers. Each word line corresponds to a respective row ofmemory cells, and each bit line corresponds to a respective column ofmemory cells. The choice of N and M depends on the memory requirementsfor a particular application. For example, N may be 256, 512, or othervalue and may include additional rows of memory cells for redundancy.Correspondingly M may be 256, 512, 1024, or other value and may includeother columns of memory cells for redundancy or parity bits for errorcorrection (ECC) memory. For example, N may be 256 or 512 and M may2304, where 256 columns are dedicated to ECC parity bits

The memory circuit of FIG. 1 also includes row decode and drive circuit114 to select appropriate word lines in response to applied addresssignals. A source line (SL) decode circuit 116 decodes applied addresssignals to control source line bias circuits 104 and 110 and may includecorresponding control logic. High voltage drive circuit 118 decodes andapplies high voltage signals to selected control gates (CG) and erasegates (EG) for programming and erasing memory cells of blocks 106 and108. Circuit 112 applies write drive (WRDRIVE) signals to write date tothe memory cells. Circuit 112 also includes an 8:1 multiplex circuit toselectively couple a local bit line (LBL) signal to a global bit line(GBL). The global bit line is selectively coupled to a sense amplifierin circuit 122 by global bit line multiplexer GMUX. After amplification,data signals are subsequently multiplexed by a read multiplex (RMUX)circuit to input/output (I/O) terminals of the SoC.

Referring next to FIG. 2, there is a simplified circuit diagram ofmemory blocks 106 and 108 of FIG. 1. Block 106 is coupled to receiveword lines WL₀ through WL_(N/2-1) and control gate leads CG₀ throughCG_(N/2-1). Block 106 is also coupled to receive bit lines BL₀ throughBL_(M-1). Block 106 includes a memory cell formed at each intersectionof a respective word line and bit line such as the memory cell formed bytransistors 200 and 202 and the memory cell formed by transistors 204and 206. Transistor 202 provides access to floating gate transistor 202Likewise, transistor 204 provides access to floating gate transistor206. Transistors 202 and 206 have control gates coupled to receivesignals CG₀ and CG_(N/2-1), respectively. Transistors 202 and 206 alsohave respective floating erase gates (EG) indicated by dashed lines asis known in the art. The source of each floating gate transistor ofblock 106 is coupled to source line SL₁₀₄ from SL BIAS circuit 104.

Block 108 is similar to block 106 and is coupled to receive word linesWL_(N/2) through WL_(N-1) and control gate leads CG_(N/2) throughCG_(N-1). Block 108 is also coupled to receive bit lines BL₀ throughBL_(M-1), which are shared with block 106. A memory cell is formed ateach intersection of a respective word line and bit line of block 108such as the memory cell formed by transistors 208 and 210 and the memorycell formed by transistors 212 and 214. Transistor 208 provides accessto floating gate transistor 210. Likewise, transistor 212 providesaccess to floating gate transistor 214. Transistors 210 and 214 havecontrol gates coupled to receive signals CG_(N/2) and CG_(N-1),respectively. Transistors 210 and 214 also have respective floatingerase gates (EG) indicated by dashed lines as is known in the art. Thesource of each floating gate transistor of block 108 is coupled tosource line SL₁₁₀ from SL BIAS circuit 110.

Turning now to FIG. 3, there is a circuit diagram of source line (SL)bias circuits 104 and 110 of FIG. 1 coupled to respective memory blocks106 and 108. In the following discussion, transistor sizes are providedas width/length (W/L) in units of micrometers by way of explanation. Oneof ordinary skill in the art will understand that these transistor sizesare only provided by way of example and may vary with different valuesof N and M (FIG. 1). SL bias circuit 104 includes n-channel transistor300 (3.9/0.4) connected in series with n-channel transistor 302(1.95/0.07) between supply voltage leads VDD (horizontal line) and VSS(small triangle). SL bias circuit 104 also includes n-channel transistor304 (3.0/0.07) connected in series with n-channel transistor 306(1.0/1.0) between source line SL₁₀₄ and supply voltage lead VSS. Acommon terminal 301 of transistors 300 and 302 is connected to a commonterminal of transistors 304 and 306. SL bias circuit 110 is similar toSL bias circuit 104 and includes n-channel transistor 310 (3.9/0.4)connected in series with n-channel transistor 312 (1.95/0.07) betweensupply voltage leads VDD and VSS. SL bias circuit 110 also includesn-channel transistor 314 (3.0/0.07) connected in series with n-channeltransistor 316 (1.0/1.0) between source line SL₁₁₀ and supply voltagelead VSS. A common terminal 311 of transistors 310 and 312 is connectedto a common terminal of transistors 314 and 316.

Operation of SL bias circuit 104 is similar to operation of SL biascircuit 110, so only operation of SL bias circuit 104 will be describedin detail. Transistor 300 is coupled to receive control signal VSF104,and transistor 302 is coupled to receive complementary control signalVSF104_OFF. When memory sector 102 is not accessed, control signalsVSF104 and VSF104_OFF are low and high, respectively. Thus, transistor300 is off, transistor 302 is on, and lead 301 is driven to supplyvoltage VSS. Control signal VRD_BUF is held high, so transistors 304 and306 are both on, and transistor 304 drives SL₁₀₄ to supply voltage VSSat lead 301. In the same manner, control signals VSF110 and VSF110_OFFare low and high, respectively, and transistor 314 drives SL₁₁₀ tosupply voltage VSS at lead 311.

When a memory cell of block 108 is accessed in a read mode, controlsignals VSF110 and VSF110_OFF remain low and high, respectively, andSL₁₁₀ remains at supply voltage VSS. Control signals VSF104 andVSF104_OFF, however, transition to high and low levels, respectively.Thus, transistor 300 is on and transistor 302 is off. Transistor 300acts as a source follower and drives lead 301 to an n-channel transistorthreshold voltage below supply voltage VDD (VDD−Vtn). Control signalVRD_BUF remains high, so transistors 304 and 306 are both on. Thus,transistor 304 drives SL₁₀₄ to VDD−Vtn. Transistor 306 is a relativelyhigh resistance transistor and acts as a bleeder or keeper device toassure lead 301 does not rise above VDD−Vtn.

SL bias circuits of the present invention are highly advantageous forseveral reasons. First, access time to a memory cell in block 108 is notcompromised, since SL₁₁₀ is held at supply voltage VSS during a readoperation. Second, SL₁₀₄ is raised to VDD−Vtn when the memory cell inblock 108 is accessed. Thus, memory cells in block 106 connected to thesame bit line as the accessed memory cell of block 108 have greatlyreduced leakage current. A typical read current of an erased memory cellis approximately 25 μA. The present inventors have determined thatleakage of unselected memory cells on a selected bit line of the priorart, however, may be as much as 16 μA/kbit. This excessive leakagecurrent adversely affects the signal-to-noise ratio (SNR) of data froman accessed memory cell. By further investigation, the present inventorshave determined that raising a source line of unselected memory cells ona selected bit line by as little as 200 mV above supply voltage VSS willreduce leakage current by approximately two orders of magnitude (100×),thereby greatly improving the SNR of the accessed memory cell. Third,source follower transistor 300 quickly drives lead 301 to VDD−Vtn, soleakage current is reduced prior to sensing data from the accessedmemory cell. Fourth, transistor 302 assures that lead 301 will not riseto a level greater than VDD−Vtn to adversely affect reliability.Finally, the SL bias circuits of the present invention produce no staticpower dissipation. Moreover, SL bias circuits such as SL bias circuit104 may include several circuits such as transistors 300 through 306,wherein each individual SL bias circuit is decoded by appropriate columnaddress signals. Thus, source line capacitance driven by each SL biascircuit may be limited to memory cells of a few respective bit lines ofa respective sector.

Turning now to FIG. 4, is a circuit diagram showing operation of memorysector 102 of FIG. 1 during a memory read operation according to thepresent invention. Operation of the circuit will be explained withreference to the timing diagram of FIG. 5 for a read operation of thememory cell at the intersection of WL₀ and BL₀. In the followingdiscussion, transistors 400 and 402 represent all lumped memory cells inblock 106 connected to BL₀. Transistors 404 and 406 represent all lumpedmemory cells in block 108 connected to BL₀. Initially, VSF104 and VSF110are low (0.0 V) and VSF104_OFF and VSF110_OFF are high (1.2 V). VRD_BUFis high (3.0 V), so transistors 304, 306, 314, and 316 are on. Sourcelines SL₁₀₄ and SL₁₁₀, therefore, are held at VSS (0.0 V) by transistors304 and 314, respectively. At time t0, VSF110 goes high (1.2 V), andVSF110_OFF goes low (0.0 V). As previously discussed, this drives SL₁₁₀to VDD−Vtn (0.6 V). As a result, current I_(LEAK) through memory cell404/406 is substantially zero. At time t1, word line WL₀ goes high (1.3V) and turns on access transistor 200 (FIG. 2). As a result, currentT_(READ) flows through memory cell 200/202, and current I_(LEAK)×(N/2−1)flows through the unselected memory cells of block 106 connected to bitline BL₀. For large N, therefore, leakage current due to unselectedmemory cells connected to bit line BL₀ is advantageously reduced byhalf. Bit line BL₀ is selectively coupled to one input terminal of senseamplifier 412 by local bit line multiplex circuit 408 and global bitline multiplex circuit 410. Reference current source 414 is coupled tothe other input terminal of sense amplifier 412. Sense amplifier 412 isinitially precharged high, so the differential current at the inputterminals produces a differential input voltage. At time t2, senseamplifier enable signal SAEN goes high (1.2 V) to amplify the differencevoltage. Read multiplex circuit 416 selectively applies the amplifieddifference voltage (DATA) to output circuit 122.

As previously discussed, SL bias circuits of the present inventionsubstantially improve the SNR at the sense amplifier. For example, ifthere are 256 memory cells on BL₀ (N=256), in each of blocks 106 and108, leakage current is reduced from 8 μA to 4 μA through BL₀. Readcurrent remains approximately 25 μA, so net current at the senseamplifier is 21 μA rather than 17 μA. This is a 24% improvement insignal strength at the sense amplifier. Of course, further SNRimprovement is possible by increasing the number of blocks per sector,thereby increasing the number of source lines per bit line. For example,if there are four blocks in a sector with 128 memory cells on eachsource line, leakage current is reduced from 8 μA to 2 μA through BL₀.Read current remains approximately 25 μA, so net current at the senseamplifier is 23 μA rather than 17 μA. This is a 35% improvement insignal strength at the sense amplifier.

Still further, while numerous examples have thus been provided, oneskilled in the art should recognize that various modifications,substitutions, or alterations may be made to the described embodimentswhile still falling with the inventive scope as defined by the followingclaims. For example, other circuit components may be used to increasethe source line voltage of unselected memory cells on a selected bitline. Moreover, embodiments of the present invention are equallyapplicable to other memory circuits such as read only memory (ROM)circuits. Embodiments of the present invention may also be applied tostatic random access memory (SRAM) circuits or various logic circuits toreduce standby current. Other combinations will be readily apparent toone of ordinary skill in the art having access to the instantspecification.

1-4. (canceled)
 5. A memory array, comprising: a word line; a bit line;a plurality of memory cells, wherein each memory cell has a firstterminal connected to the bit line and a current path between the firstterminal and a respective second terminal; a first memory cell of theplurality of memory cells having the second terminal coupled to receivea first supply voltage when selected by the word line; and a secondmemory cell of the plurality of memory cells having the second terminalcoupled to receive a voltage different from the first supply voltagewhen the first memory cell is selected by the word line; a firsttransistor having a current path coupled between a second supply voltageterminal and a common terminal; a second transistor having a currentpath coupled between the common terminal and a terminal having the firstsupply voltage; a third transistor having a current path coupled betweenthe second terminal and the common terminal; and a fourth transistorhaving a current path coupled between the common terminal and theterminal having the first supply voltage.
 6. The memory array of claim5, wherein the first transistor is arranged to operate as a sourcefollower.
 7. (canceled)
 8. A memory array, comprising: a plurality ofmemory cells, each memory cell having a first terminal, a secondterminal, and a control terminal arranged to control current flowbetween the respective first and second terminals; a plurality of bitlines connected to first terminals of respective memory cells; and abias circuit arranged to apply a supply voltage to the second terminalsof the memory cells in a first mode of operation and to apply a biasvoltage different from the supply voltage to the second terminals in asecond mode of operation.
 9. The memory array of claim 8, wherein thefirst mode is an active mode of operation and the second mode is astandby mode of operation.
 10. The memory array of claim 8, wherein thefirst mode is a selected mode of operation and the second mode is anunselected mode of operation.
 11. The memory array of claim 8, whereinthe bias voltage is substantially equally to a second supply voltageless a transistor threshold voltage
 12. The memory array of claim 8,wherein the memory cells are flash electrically programmable erasablememory cells.
 13. The memory array of claim 8, wherein the memory cellsare read only memory (ROM) cells.
 14. The memory array of claim 8,wherein the memory cells are static random access memory (SRAM) cells.15. The memory array of claim 8, wherein a first memory cell of theplurality of memory cells has a first terminal connected to a first bitline and a second terminal coupled to receive the supply voltage whenselected in a read mode, and wherein a second memory cell of theplurality of memory cells has a first terminal connected to the firstbit line and a second terminal coupled to receive the bias voltage whenthe first memory cell is selected is selected in the read mode.
 16. Thememory array of claim 8, wherein the bias circuit comprises: a firsttransistor having a current path coupled between a second supply voltageterminal and a common terminal; a second transistor having a currentpath coupled between the common terminal and a terminal having thesupply voltage; a third transistor having a current path coupled betweenat least one of the second terminals and the common terminal; and afourth transistor having a current path coupled between the commonterminal and the terminal having the supply voltage.
 17. A method ofoperating a memory array, comprising the steps of: connecting a firstterminal of each of a first plurality and a second plurality of memorycells to a bit line; applying a supply voltage to a second terminal ofeach memory cell of the first plurality when at least one of the memorycells of the first plurality is selected; and applying a bias voltage toa second terminal of each memory cell of the second plurality when theat least one of the memory cells of the first plurality is selected. 18.The method of claim 17, comprising applying the supply voltage to thesecond terminal of each memory cell of the second plurality when nomemory cell of the first plurality is selected.
 19. The method of claim17, comprising: applying the bias voltage to the second terminal of eachmemory cell of the first plurality when at least one of the memory cellsof the second plurality is selected; and applying a supply voltage tothe second terminal of each memory cell of the second plurality when theat least one of the memory cells of the second plurality is selected.20. The method of claim 17, wherein the second terminal of each of thefirst plurality of memory cells is a first common source lead, andwherein the second terminal of each of the second plurality of memorycells is a second common source lead.